Investigation of Gate Underlap Design on Linearity of Operational Transconductance Amplifier (OTA)

The significance of optimization of gate–source/drain extension region (also known as underlap design) in double gate (DG) silicon-on-insulator (SOI) FETs to improve the linearity performance of a low power folded cascode operational transconductance amplifier (OTA) is described. Based on a new figure-of-merit (FoM) involving AV , linearity, fT and dc power consumption PDC , the paper presents guideline for optimum design for underlap spacer s and film thickness Tsi to maximize the performance of OTA. It has been shown that FoM exhibited by an underlap DG MOSFET OTA gives significantly higher value ( ≅ 9) compared to a conventional single gate bulk MOSFET OTA. This is due to a combination of both higher fT, and higher gain AV for the same linearity at low power consumption of 360μW. With gate length scaling, FoM continues to improve, primarily due to higher value of fT. A scaled bulk MOSFET OTA exhibits similar but much smaller enhancement in trend for FoM